1. Field of the Invention
The present invention relates to a signal processing circuit used for a digital serial interface, more particularly relates to a data cipher circuit.
2. Description of the Related Art
As an interface for multimedia data transfer, an IEEE (The Institute of Electrical and Electronic Engineers) 1394 high performance serial bus which realizes high speed data transfer and real-time transfer has recently been standardized.
The data transfer by the IEEE 1394 serial interface includes the conventional asynchronous transfer for making requests, acknowledging requests, and acknowledging receipt and isochronous transfer wherein data is always sent once per 125 μs from a certain node.
In the IEEE 1394 serial interface having such two transfer modes, data is transferred in units of packets.
FIGS. 10A and 10B are views of a byte size of one source packet in the isochronous transfer. FIG. 10A shows the packet size in a digital video broadcast (DVB) specification and FIG. 10B shows the packet size in a digital satellite system (DSS) specification.
The source packet size in the DVB specification is, as shown in FIG. 10A, 4 bytes of a source packet header (SPH) plus 188 bytes of transport stream data, that is, 192 bytes.
The source packet size in the DSS specification is, as shown in FIG. 10B, 4 bytes of a source packet header (SPH), 10 bytes of added data, and 130 bytes of data, that is, 144 bytes.
The added data is inserted between the source packet header and the data. Note that since the unit of maximum data to be handled is 1 quadlet (=4 bytes=32 bits) in the IEEE 1394 standard, it is necessary to set things to enable the sum of the transport data and the added data to be configured in units of 32 bits.
Note that it can be set without the added bytes at default.
FIG. 11 is a view of an example of the correspondence of original data at the time of transferring data by isochronous communication of the IEEE 1394 standard and packets actually transferred.
As shown in FIG. 11, a source packet of the original data is given 4 bytes of the source packet header and padding data for adjusting the data length, then is divided into a predetermined number of data blocks.
Note that since the unit of data at the time of transferring a packet is 1 quadlet (4 bytes), the byte length of the data block and a variety of headers are set to be multiples of 4.
FIG. 12 is a view of the format of a source packet header.
As shown in FIG. 12, a time stamp used for controlling jitter is written in 25 bits in the source packet header, for example, when MPEG (Moving Picture Experts Group)-TS (transport stream) data used in digital satellite broadcasts etc. of the above DVB mode is transferred by isochronous communication.
Then, data such as the packet header, common isochronous packet (CIP) header, etc. is added to a predetermined number of data blocks to generate a packet.
FIG. 13 is a view of an example of the basic configuration of a packet in isochronous communication.
The packet in isochronous communication is configured, as shown in FIG. 13, of a first quadlet comprising a 1394 header, a second quadlet comprising a header-CRC, a third quadlet comprising a CIP header 1, a fourth quadlet comprising a CIP header 2, a fifth quadlet comprising a source packet header (SPH), and a sixth quadlet on comprising a data region. The last quadlet comprises a data-CAC.
The 1394 header is composed of a data-length region indicating the data length, a channel region indicating the number of the channel to which the packet is transferred (one of 0 to 63), a tcode region indicating a processing code, and a synchronization code sy region defined by the application.
The header-CRC is an error detection code of the packet header.
The CIP header 1 is configured by a source node ID (SID) region for a transfer node number, a data block size (DBS) region for a data block length, a fraction number (FN) region for a fraction number of data in making a packet, a quadlet padding count (QPC) region for a quadlet number of padding data, an SPH region for a flag indicating an existence of a source packet header, and a data block continuity counter (DBC) region for a counter for detecting a number of isochronous packets.
Note that the DBS region indicates the number of quadlets to be transferred in one isochronous packet.
The CIP header 2 is composed of an FMT region for a signal format indicating a kind of data to be transferred and a format dependent field (FDF) region used corresponding to a signal format.
The SPH header includes a time stamp region in which is set a value for giving a fixed delay value at the time when a transport stream packet arrives.
The data-CRC is an error detection code of a data field.
A signal processing circuit of the IEEE 1394 serial interface for transfer of a packet having the above configuration is composed of, as shown in FIG. 14, a physical layer circuit 1 for directly driving an IEEE 1394 serial bus and a link layer circuit 2 for controlling the data transfer of the physical layer circuit 1.
In the above isochronous communication system of the IEEE serial interface, for example as shown in FIG. 14, the link layer circuit 2 is connected to the serial interface bus BS via the physical layer circuit 1.
Also, the link layer circuit 2 is connected to an application side circuit 3 such as an MPEG transporter, a digital video cassette recorder (DVCR), etc.
Currently, video data of movies and TV broadcasts is made unable to be freely, digitally recorded in the home etc. in order to prevent illicit copying infringing copyrights etc. Therefore, for example, a set-top box for receiving digital satellite broadcasts is not provided with a digital output terminal.
However, an IEEE 1394 serial interface is an interface for transmitting digital data of video, music, etc. between separate apparatuses. Furthermore, with home use digital recording apparatuses being actively developed and offered for practical use, an increase of opportunities for digital recording at the home etc. is inevitable.
Therefore, considering such a situation, a function for effectively preventing illicit copying is thus necessary. No configuration provided with this function has yet been realized in signal processing circuits of IEEE 1394 serial interfaces.
Also, when realizing such encipher functions, it is necessary to prevent the problem, at the time of successively transmitting a plurality of packet data, of the receiving side becoming unable to discriminate the cipher mode and unable to decipher when data enciphered in different cipher modes exist together in one transmission cycle.